期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：4
页码：1260-1262
出版社：Shri Pannalal Research Institute of Technolgy
摘要：This paper describes design and implementation of logical scrambler architecture for OTN protocol and specifications of their logical resources. The logical scrambler architecture can be designed using serial scrambler architecture, in which registers are connected in parallel to achieve high data transfer rate in OTN protocol. The whole design will be developed using Xilinx ISE 12.2 and will be simulated using Modelsim 6.3c and will be implemented on Virtex 4 FPGA.
