期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：5
页码：1620-1623
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The current fad of reducing the chip area and optimizing power dissipations of SRAM cells has led to rapid MOSFET channel length scaling down. But stability remains a factor to be considered. Optimizing parameters like Static Noise margin, Read Margin, Write Margin are paramount to obtain desirable characteristics of SRAM cells. This paper presents the parametric analysis of different configurations of SRAM memory cells such as ¨C 6T, 7T, 8T, 9T and 10T. The parameters analyzed are Static Noise Margin (SNM), Write Margin, Read Margin and Data Retention Voltage (DRV). The analysis is done using Tanner EDA Tool on 250nm technology at a supply voltage of 5.0 volts.
