期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：5
页码：1660-1665
出版社：Shri Pannalal Research Institute of Technolgy
摘要：This paper describes a longest test path selection based on gate delay and probabilistic approach by considering a path delay in a digital circuit. Various methods on longest test path selection are adopted such as longest transition path, segment coverage and heuristics. Preprocessing of Circuit Under Test (CUT) is done for reducing test time and to achieve low power consumption using BIST implementation. Accumulation of small delay defects on a path is identified by computing probability of particular path to meet the delay constraint. Th us the probability is estimated based on gate delay of each path in a digital circuit. Longest path selection approach is mainly chosen to trace out all the logical elements in the circuit. Delay occurs in the circuit due to various factors such as gate delay, interconnect delay, etc. In proposed method longest test path delay is selected from circuit switching activity which is caused mainly due to gate delay.
关键词：path correlation; test path selection; BIST; upper ; and lower bound; path delay; probability
