期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：6
页码：2141-2145
出版社：Shri Pannalal Research Institute of Technolgy
摘要：In shared bus architecture arbiter module plays a vital role in resolving contention between different masters to get the access for the bus. The arbiter along with resolving contention must also provide fair bandwidth allocation to each master meeting its real time requirements. In this project arbitration algorithm, taking into consideration real time requirement of masters was implemented for Advanced Microcontroller Bus Architecture (AMBA) protocol. Real time masters are given higher priority over their non-real time counterpart, and the blocking is mitigated by assigning a warning zone to the later. Clock gating technique is employed to lower dynamic power dissipation of the arbiter module. The module is designed using verilog HDL on a Xillinx 13.1 platform, and synthesis was done using Cadence RC compiler. Finally physical designing of the arbiter module was done using Cadence encounter digital implementation tool. Results obtained indicate that the proposed technique allocates fair bandwidth to all masters in the system at the same time meeting real time requirement of the masters aspiring to get access of the bus. Total power dissipation, as well as dynamic power dissipation of the module is found to be lower due to clock gating technique.
