期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：11
页码：4026-4029
出版社：Shri Pannalal Research Institute of Technolgy
摘要：This paper proposes a novel approach to design high speed, low power self triggered D flip-flops with extremely small die area in comparison to the conventional flip-flops. Flip-flops are synchronous sequential machines that require an external clock pulse for synchronization. The proposed flip-flop generates an internal clock itself and due to this flip-flop does not require external synchronization. Proposed design has relatively less number of transistors than conventional designs, which drastically improved the performance in terms of compactness, speed and power consumption. Design and simulation of proposed flip-flop has been carried out in Microwind simulation tool using 90 nm CMOS technology.
关键词：Self Triggered; CMOS; die area; power ; consumption; transistor count
