期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2014
卷号：3
期号：12
页码：4362-4367
出版社：Shri Pannalal Research Institute of Technolgy
摘要：In this paper we have presented the design of a low-pow er full subtractor circuit using P-XOR/ G-XNOR pass transistors logic gates. The main aim of designing the low power full subtractor circuit is the increasing circuit's complexity and demand of portable devices. Full subtractor circuit is one of the main components of most of the arithmetic and logic circuits. Full subtractor circuit is implemented using one or more XOR/ XNOR gates which consume the large part of the energy. The main objective of the work is to reduce the power of the circuit either by reducing the number of XOR/ XNOR gate or by using P-XOR/ G-XNOR logic gates which consumes less power in comparison with the conventional XOR/ XNOR gates.
关键词：Arithmetic and Logic circuits; Conventional ; XOR/ XNOR gates; Full subtractor; Low power; ; Pow erless (P)-XOR/ Groundless (G)-XNOR gates
