期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2015
卷号：4
期号：4
页码：1394-1397
出版社：Shri Pannalal Research Institute of Technolgy
摘要：the growing technology trends of extremely low power opera ted handy applications like PC, note book, smart phones and other electronic gadgets requires microelectronic devices w ith low power consumption. It is obvious that the transistor dimensions goes on to shrink and as require for more complex chips to increases and as a consequence power organization of such deep sub-micron based chip is one of the major issue in VLSI industry. The manufacturers are always concentrated for low power designs to provide adequate physical resources to withstand against design hurdles and this lead to increases the cost and restrict the functionality of the device. This power reduction ratio is the highest among FFs and their related designs like RAM, ROM and CAM that have been reported so far. Therefore pow er reduction is the critical issue at design level. It is familiar that Content addressable memory (CAM) offers high-speed search function in a single clock cycle. Due to its parallel match-line contrast, CAM is more power dissipative unit. Accordingly, strong, high-speed and low-pow er sense amplifiers are extremely required in CAM designs. In this document, we proposed a new CAM structure which drastically reduces more than 40% sensing delay and overall power consumption is stagnant with gating technique. The performance of this paper is evaluated on the design simulation using Microw ind 3.1 simulator with 32nM CMOS design.
