期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2015
卷号：4
期号：5
页码：1833-1837
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The logarithmic number system can be used in various ways to represent the data in efficient way which is used in various special purpose VLSI processors. The LNS exploits the property to reduce the basic arithmetic function of division, roots multiplication and powers to binary subtraction, addition and left and right shifts respectively. Furthermore, the LNS also provides additional benefit as it gives us freedom to choose the logarithmic base. In this paper, basic architecture of LNS adder/subtractor consist of adder, multiplexer and 2 look up tables(LUT) which are named as addition LUT and subtraction LUT. Power dissipation is done by partitioning the LUT's into sub -lut's and further dividing into 4 lut's. Partitioning of LUT is done to create parts in circuits to help in achieving power dissipation. only one of sub-lut is activated upon on each operation which depends on MSB or LSB and also on the sign of operands. Power dissipation can further be reduced by using D-FF since they allow more than one MSB to break the lut's. The performance has been measured in terms of delay, power, area with logical effort and Xilinx ISE 14.4(Verilog HDL).
