期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2015
卷号：4
期号：6
页码：2838-2841
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Carry select adder is one of the key hardware block in most of arithmetic logic unit and arithmetic logic is the essential unit of the microprocessors, DSPs and FIR filters etc. In the world of technology it has become necessary to develop several innovative design approaches to decrease the area and power consumption. In this paper TG has been used to develop the proposed 64-bits CSA using AND, XOR and OR gates. The main objective of this paper is to design a new CSA which gives better results in terms of delay and power dissipation than the conventional CSA designs. The proposed 64-bits CSA has been designed using 45nm, 90nm and 180nm CMOS technologies and we use TANNER tool version 7 for circuit implementation. The developed adder has shown the improvement in delay and average power consumption in order to implement CSA adder proficiently in digital signal processors.
