期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2015
卷号：4
期号：10
页码：3990-3994
出版社：Shri Pannalal Research Institute of Technolgy
摘要：ADDER is an important block in digital system. It has applications in digital signal processing to perform finite impulse response and infinite impulse response. Ripple carry adder speed will be disadvantage but area will be les s when compared to carry look ahead adder in which area will be the disadvantage but speed will be the advantage. Now we have got the challenge that is to reduce the area but speed should be retained that is carry should be designed separately for generate part and propagate part, so with this two design constraints area and speed are going to be achieved but never the less third important design constraint is power consumption of the circuit which by default will be achieved as we are designing the circuit by using STATIC CMOS. In this project the proposed Adder has been designed by using STATIC CMOS 180nm TECHNOLOGY and the tool being used is TANNER EDA tool.
