期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：3
页码：248-253
出版社：Shri Pannalal Research Institute of Technolgy
摘要：This paper presents the implementation of March Algorithm based Memory Built-In Self Test (MBIST) architecture for Static Random Access Memory (SRAM). A Finite State Machine (FSM) is designed to implement March ¨C based Test algorithm. Also SRAM block and the interfacing modules are presented. There is a standard March Test Algorithm with 22N where N is the number of memory words, read/write operations is discussed. The proposed March test algorithm with 13N can achieve full diagnosis for SRAM. This digital system is described in Verilog HDL and is simulated and synthesized using Xilinx Spartan 3 FPGA. The proposed scheme greatly simplifies the testing process. Besides, the proposed scheme is more efficient in terms of circuit size and test data to be applied, and it requires less time to test SRAM chip. Power consumption of a digital system is nearly fifteen times mo re in test mode when compared with normal mode. Power consumption is greatly reduced in this proposed architecture by reducing number of read/write operations. Experimental results show that the proposed method achieves a good flexibility with smaller circuit size.
