期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：4
页码：476-479
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The complexity in implementing complex logic functions in hardware circuitry is to be reduced in order to perform large calculations with minimum delay. This paper presents a most efficient and high speed design for doubling a binary number using Dwandwa Yoga logic, a squaring algorithm. The calculation is performed based on the "Duplex" D property. This method reduces the carry propagation delay when compared to the other vedic multiplication algorithms and conventional multiplication algorithms to a great extent. As the number of bits increases the size of the hardware circuitry decreases to a great extent by using the proposed logic. For the same number of bits, the dwandwa yoga requires less number of calculations compared to Urdhva tiryakbhyam. This design can be further used in apllications where low power and small area are main criteria.
