期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：4
页码：575-579
出版社：Shri Pannalal Research Institute of Technolgy
摘要：This paper covers the implementation of the implementation of Network Intrusion Detection System (NIDS) using International Data Encryption Algorithm (IDEA). The current era has seen an explosive growth in communications. Applications like online banking, personal digital assistants, mobile communication, smartcards, etc. have emphasized the need for security in resource constrained environments. International Data Encryption Algorithm (IDEA) cryptography serves as a perfect network intrusion detection system (NIDS) tool because of its 128 bits key sizes and high security comparable to that of other algorithms. However, to match the ever increasing requirement for speed in today's applications, hardware acceleration of the cryptographic algorithms is a necessity. This study presents an efficient hardware structure for the modulo (2n+ 1) Multiplier, which is the most time and space consuming operation in IDEA. The proposed modulo multiplier saves more time, area and cost. The block size considered here is same as of traditional IDEA encryption algorithm which is of 64 bits with 16 bit sub-blocks.
关键词：NIDS; IDEA; Crptography; mobile communication; Modulo (2n+ 1) Multiplier
