期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：5
页码：241-250
出版社：Shri Pannalal Research Institute of Technolgy
摘要：The proposed architecture consists of an efficient VLSI hardware implementation of the Modified Genetic Algorithm for identifying the good pulse compression sequences based on Discrimination Factor. The main advantage of implementation using Hardware based Genetic Algorithm is its inherent speed over Software based methods. The speed advantage makes the hardware based Modified Genetic Algorithm (MGA) is a prime candidate for real time applications. This architecture provides the flexibility of generating Pulse compression sequences with variable frequencies. Radar signal processing applications require a set of sequences with individually peaky auto correlation and pair wise cross correlation. Obtaining such sequences is a combinatorial problem. If the auto correlation and cross correlation are taken in the aperiodic sense then there are hardly any theoretical aids available. Thus the problem of signal design referred to above are challenging problem for which many global optimization algorithms like genetic algorithm, simulated annealing, tunneling algorithm were reported in the literature. Higher performance systems using custom silicon cost too much for the typically small production volumes, and are not flexible enough for research applications. Field programmable gate arrays offer the performance of custom silicon while maintaining the economies and flexibility of the microprocessor based solutions. Recent FPGA devices possess the density and performance to realize Pulse compression sequences in a single FPGA. The Proposed VLSI architecture is implemented on the FPGA as it provides the flexibility of re-configurability and re- programmability. The Proposed architecture is a novel and efficient architecture as it generates the Pulse compression sequences at the clock rate of FPGA.
