期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：5
页码：274-279
出版社：Shri Pannalal Research Institute of Technolgy
摘要：A full adder is one of the essential component in digital circuit design, many improvements have been made to reduce the architecture of a full adder. The proposed method aims on Gate diffusion input (GDI) which is a low power technique to design any digital system. Mostly 90% of the power consumption is due to of dynamic behavior of the circuit. Dynamic component of power is reduced in GDI technique as the source of PMOS is not permanently connected to Vdd, and it also reduces the latency of the circuit .In this paper we introduce a novel low power and Area efficient Carry Look Ahead Adder using refined full adder. The results shows that the designed adders have superior performance compared with the existing adders in terms of power dissipation and transistor count. The design is simulated using Mentor graphics tool with a supply voltage of 5V.
