期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：5
页码：346-351
出版社：Shri Pannalal Research Institute of Technolgy
摘要：A radix-4/-8 multiplier is implemented using modified booth multiplier encoder that demand high speed and low energy operation. Depending on the input pattern, the multiplier operates in the radix-8 mode in 56% of the input cases for low power, but reverts to the radix-4 mode in 44% of the slower input cases for high speed. The performance of the radix-8 multiplier is bottlenecked due to the occurrence of the 3B term in computing the partial products. So for computing the partial product in this case we select the radix-4 mode. It is a good approach if we implement the multiplier as a hybrid architecture of the radix-4/-8 because the radix-8 mode has low power consumption capability, occupying less area and the main advantage is that the number of partial products obtained in this mode are less(N/3) compared to the partial products of the radix-4 mode(N/2). But the detection of the 3B term while computing the partial products is very difficult and it is difficult to implement it on the FPGA board. So by comparing the performances of the two multipliers we suggest to go with the radix-4 multiplier and it is implemented here. In this paper we are implementing the radix-4 multiplier along with the MAC(Multiplier and Accumulator) unit for computing the signal values in real time applications. The carry save adder block is selectively activated to reduce power consumption. This is implemented on XC3S200 FPGA. It consists of 3840 LUT's of 4-input out of which only 550 LUT's are used and also it consists of 173 IOB's out of which only 66 are used. This project is implemented on Xilinx XC3S200 FPGA and is simulated using VHDL and synthesized using Xilinx 12.1.
