期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2012
卷号：1
期号：6
页码：1-6
出版社：Shri Pannalal Research Institute of Technolgy
摘要：In this paper, we present a work of new hardware architecture to a Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection. Here, we anticipate that optimizations in terms of power consumption will significantly improve the architecture. Because of optimization of architecture, we get a new hardware, which consumes less amount of power than previous hardware architecture.Real-time object detection is becoming necessary for a wide number of applications related to computer vision and image processing, security, bioinformatics, and several other areas. Existing software implementations of object detection algorithms are constrained in small-sized images and rely on favorable conditions in the image frame to achieve real- time detection frame rates. Efforts to design hardware architectures have yielded encouraging results, yet are mostly directed towards a single application, targeting specific operating environments. Consequently, there is a need for hardware architectures capable of detecting several objects in large image frames, and which can be used under several object detection scenarios.In this work, we present a generic, flexible parallel architecture, which is suitable for all ranges of object detection applications and image sizes. The architecture implements the AdaBoost-based detection algorithm, which is considered one of the most efficient object detection algorithms. Through both field-programmable gate array emulation and large-scale implementation, and register transfer level synthesis and simulation, we illustrate that the architecture can detect objects in large images (up to 1024 . 768 pixels) with frame rates that can vary between 64¨C139 fps for various applications and input image frame sizes.
