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  • 标题:Design of Transposed Polyphase Decimation Filter Using Dadda Multiplier
  • 本地全文:下载
  • 作者:M.Ramya ; S.Jeevitha ; T.Kowsalya
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2015
  • 期号:MULTICON
  • 页码:381
  • 出版社:S&S Publications
  • 摘要:Power has become a major issue in modern vlsi design. in digital signal processing systems, multiplierplays an important role but also it consumes more power and area. while using bfd multiplier for designing transposedpolyphase decimation filter, it has more dynamic power dissipation which is due to the increased switching activityduring multiplication and consumes a large circuit area. also, the number of addition depends on the number ofmultiplicand bits which cannot be reduced. to overcome these drawbacks, dadda multiplier is used for betterperformance as much as compared to existing system.
  • 关键词:Polyphase decimation filter; Dadda Multiplier architecture; Power dissipation; Carrylook ahead adder;speed.
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