期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
期号：MULTICON
页码：552
出版社：S&S Publications
摘要：In recent years, total power dissipation and area are one of the most important challenges in VLSIdesign. By reducing the number of transistors in the circuits and the design structures are may occupied small area andultra-low power design. In this project based on AND gates and full adders are designed using pass transistor logic(PTL) and different techniques are used for low power in AND Gate, full adder and multipliers. The main aim of thispaper is to reduce the power dissipation and area by reducing the transistors. In this project various types of parallelmultiplier designs are performed. Multipliers are the major sources of power dissipation in DSP applications. Thedesign analysis of delay and power comparison of the low power using different types of AND gates and multipliers.The designs are implemented delay and power results are obtained using Mentor Graphics EDA tool. The modeltechnology file 0.18 um is use this design. The results show that the transistor counts, delay and the power required aresignificantly concentrated in the design.
关键词：Pass Transistor Logic (PTL); AND gate; Full adder; Parallel Multipliers; Total Power Dissipation;Delay
