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  • 标题:Removal of Asynchronous Data Sampling Error in DET Half Static and Clock-Gated D Type Flip Flop
  • 本地全文:下载
  • 作者:V.M.SenthilKumar ; S.Saravanan ; Yazhini
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2015
  • 期号:MULTICON
  • 页码:562
  • 出版社:S&S Publications
  • 摘要:Now a days power consumption plays a vital role in VLSI circuits. The growing market of mobile,battery-powered electronic devices demands the design of electronic circuits with low power consumption. To design alow power circuit, energy efficiency from the clock element is an important issue. There is different technique for theenergy efficiency. One of the most preferred technique is double edge triggered technique (DETFFs).To reduce thedynamic power consumption clock gating is the best technique. When we combine these two techniques it reducesdynamic power but introduces asynchronous data sampling. In this paper we are discussing two different methods toavoid asynchronous data sampling.
  • 关键词:DETFF; clock-gating; asynchronous sampling..
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