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  • 标题:Floating Point Fused Add-Subtract an Fused Dot-Product Units
  • 本地全文:下载
  • 作者:S. Kishor ; S. P. Prakash
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2015
  • 期号:MULTICON
  • 页码:575
  • 出版社:S&S Publications
  • 摘要:A single precision floating-point fused add-subtract unit and fused dot-product unit is presented thatperforms simultaneous floating-point add and multiplication operations. It takes to perform a major part of singleaddition, subtraction and dot-product using parallel implementation. This unit uses the IEEE-754 single-precisionformat and supports all rounding modes. The fused add-subtract unit is only about 56% larger than a conventionalfloating-point multiplier, and consumes 50% more power than the conventional floating-point adder. The speed of thefused dot-product is about 27% faster than the conventional parallel approach. This will combine to use for FFTalgorithms mainly. The simulation results are obtained using Xilinx 14.3 EDA tool. The results show that the RTLview and synthesis reports.
  • 关键词:Fused Add-Subtract unit (FAS); Single precision floating point Dot-Product unit (FDP); Rounding;modes; Number Of LUT'S; Delay; Verilog; Xilinx
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