期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2015
期号：MULTICON
页码：741
出版社：S&S Publications
摘要：In the existing system the high amount of delay, area and power can be used . so we use a novelpartial product generator and propose a strategy for optimized balanced pipelining across the time-consumingcombinational blocks of the structure. To achieving lower adaptation-delay and area-delay-power efficientimplementation. In proposed method we use large processing elements (PEs) for achieving a lower adaptation delaywith the critical path of one MAC operation. They have proposed a fine-grained pipelined design to limit the criticalpath to the maximum of one addition time, which supports high sampling frequency, but involves a lot of area overheadfor pipelining and higher power consumption due to large number of pipeline latches. A an efficient adder tree forpipelined inner-product computation to minimize the critical path and silicon area without increasing the number ofadaptation delays. so we use a carry select adder in the proposed method to reduce the area and power. The carry selectadder is efficient adder and easy to design compare to other design.
关键词：Adaptive Filter; Least Mean Square Algorithm; Weight Update Block; Adder
