期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：3
页码：3465
DOI：10.15680/IJIRSET.2016.0503137
出版社：S&S Publications
摘要：In today’s world there's an excellent need for the design of low power and area efficient highperformance DSP system. FIRfilter is taken into account to be the elemental device within the broad application ofwireless in addition because the video and image processing system. With the aim of obtaining the reliable operation,these filters are protected exploitation the Error correction Code. The pipelined FIR filter design that reduces thecritical path by interleaving the pipelined latches on the datapath, with the sense of accelerating the quantityof latchesthen the system latency. However the parallel processed FIR filter design will increase the sample rate therebyreplicating thehardware, so the multiple range of inputs gets processed parallely and at identical time generatingmultiple varieties of outputswith the disadvantage of magnified space within the design. To overcome this disadvantageand within the sense of holding theseadvantage of multiprocessing, the hardware economical filter structure is to beproposed, and these filter structure is to be recoveredfrom error by the application of Error Correction Code.
