期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：4
页码：4955
DOI：10.15680/IJIRSET.2016.0504051
出版社：S&S Publications
摘要：In this paper we first analyse the characteristics of FPGA and puts forward fast pulse compressionarchitecture. System-level simulation using MATLAB and Verilog for space borne SAR is carried out by the new wayof system verification techniques. In anticipation of much potential joint Space-Based Radar (SBR) missions betweenthe Air Force and NASA in the future. We propose to develop an FPGA-based (field programmable- gated-array)architecture for on-board processing of radar data. In particular, the hardware is targeted for the high computational loadin processing Synthetic aperture-radar (SAR).Pulse compression plays an important role in design of the radar system.Pulse compression using linear frequency modulation techniques are very popular in modern radar. The linearfrequency modulation is done here to resolve two small targets that are located at long range with very small separationbetween them. Pulse compression technology is defined as a process that radar transmitter emits large pulse frequencymodulation signal and the receiver can obtain narrower pulse after matching and compression processing. The methodbetter resolves the contradiction between the restriction of peak pulse power and range resolution in radar. Pulsecompression actually employ matching filter for radar receiving signal. Based on the theory of matching filter, theimpulse response of filter is the conjugation of input signal. Similarly Azimuth resolution is carried out by usingAzimuth reference function.The application of this is finding the two different targets located at same place with a very small separation betweenthem. And use of doing pulse compression is use of low power in the RADAR systems.
