期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：5
页码：7241
DOI：10.15680/IJIRSET.2016.0505086
出版社：S&S Publications
摘要：The reconfigurable router for NOC has been arranged in the present business. Here the router which hasbeen planned contains four channels viz, west, east ,south and north and a solitary framework switch. An individualchannel contains MUX and FIFO memory. The information inputs and yields are confined by MUX and informationstockpiling is accomplished utilizing FIFO memory. At first, north channel is planned alongside its sub-pieces likeMUX and FIFO memory. Later the framework switch and remaining channels are planned. At last, planned channelsalongside their MUX, FIFO recollections and a grid switch are fused to diagram the whole router structure. Hereexecution of the router is completed by method for Verilog HDL. The PC created reproduction of arranged outline iscompleted with the assistance of Modelsim. The RTL perspectives are gotten with the assistance of Xilinx ISE 14.5.All out force figuring is performed utilizing Xpower Analyzer Tool.
关键词：Network on Chip(NoC); Reconfigurable Router; First in First out(FIFO) Buffer; Crossbar Switch;Multiplexer; Register Transfer Level(RTL) Design; Low Power
