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  • 标题:Implementation of Parallel Self Timed Adder Using Modified GDI Logic
  • 本地全文:下载
  • 作者:V.Preethi ; N.Subbulakshmi
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2016
  • 卷号:5
  • 期号:5
  • 页码:8562
  • DOI:10.15680/IJIRSET.2016.0505277
  • 出版社:S&S Publications
  • 摘要:This paper presents comparisons of logic style based on different logic functions in which Modified GateDiffusion Input logic (Mod-GDI) is power-efficient than Gate Diffusion Input logic (GDI) and Complementary MetalOxide Semiconductor CMOS logic design. When CMOS logic is used number of transistors increases and hence areaincreases. By using GDI logic area and power dissipation decreases but it suffers from the problem of bulk connectionsand high swing degradation. Mod-GDI is used to reduce the swing degradation problem which consists of only twotransistors, by changing its input configuration number of boolean function are obtained. The practical circuitarrangements reveal Mod-GDI to be more superior to GDI and CMOS logic with respect to speed, area, powerdissipation and power. Simulation results shows up to 50% reduction in area and power dissipation in Mod-GDI. Thislogic is used for designing fast, low power circuits with reduced number of transistor as compared to CMOS techniques,while improving power characteristics.
  • 关键词:Asynchronous logic; CMOS logic; GDI logic; Modified GDI logic.
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