期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：6
页码：11104
DOI：10.15680/IJIRSET.2015.0506199
出版社：S&S Publications
摘要：SAR ADC plays an important role in converting the analog signal to digital signals in applicationswhich require moderate speed, resolution, and low power operation at lower cost. Limitation associated withconventional SAR ADC is its resolution. This is because of the capacitive DAC employed. As the resolution of ADCincreases, the number of capacitors required for the DAC will also increases, this will lead to lot of mismatch betweenthe capacitors during fabrication process. The mismatch in the capacitors causes the non-linearity errors, more area isrequired to accommodate more number of capacitors and also consumes more power. Hence to overcome thislimitation of resolution associated with SAR ADC, different architecture of DAC is proposed and it is referred as ΔΣDAC. In ΔΣ DAC, the digital bits generated from SAR logic is converted into bit streams. The bit stream is used toestimate the corresponding analog voltage with the help of analog computation block. Working principle of ΔΣ DAC isanalyzed and verified using Verilog model. Building blocks needed to implement the 3-bit ΔΣ DAC are discussed,implemented in SPICE and the simulation results are documented. This paper consists of detailed description of theworking principle of ΔΣDAC, implementation and partial results of ΔΣDAC.
