期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：6
页码：11150
DOI：10.15680/IJIRSET.2015.0506226
出版社：S&S Publications
摘要：This paper introduces an efficient flexible architecture for error tolerant applications to implement DSPkernels. The proposed methodology is more compact than traditional arithmetic units which enable the exploitation oferror tolerant adder. The flexible architecture comprises of flexible computational units which execute large number ofoperation templates, exploits carry save format for its operations and it is based on modified booth algorithm. It is ableto handle 8 bit, 16 bit and 32 bit operations and also provides high computational density, fast operations andreusability of data. Comparing this with the existing architectures, the proposed method yields better performance interms of power, speed, and area.
