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  • 标题:Simulated High Speed Fault Injection in Arithmetic Unit using Verilog HDL
  • 本地全文:下载
  • 作者:M.B Aswini ; R. Chitra ; S. Gopika Devi
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2016
  • 期号:NCFCSPS
  • 页码:231
  • 出版社:S&S Publications
  • 摘要:In recent years, there has been a rapid increase in the use of computer-based systems in areaswhere failures can cost lives and money, such failure occurs in railway traffic control, aircraft flight,telecommunications, and others. This trend has led to a growing interest in the techniques for the validation ofthe fault tolerance properties of these systems and for the evaluation of their reliability, thus leading to a VLSItechnology where fault injection has become a popular technique for experimentally verifying the fault tolerantbased designs. In this proposed work a high speed fault injection tool for testing has been developed to build areal time fault injection mechanism with good performance in all the aspects. This paper presents a faultinjection Micro Wind Tool (FIMTO) that supports synthesizable fault models for dependability analysis ofdigital systems. As a case study, design of AU is done and the fault is injected into it.
  • 关键词:VLSI technology; Fault injection; Arithmetic Unit (AU); Fault injection Micro wind tool.
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