期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
期号：NCFCSPS
页码：257
出版社：S&S Publications
摘要：In our project, we propose a novel architecture which generates the test pattern to reduceswitching activities. The more power consumption can create problems such as immediate power endurance thatcause circuit damage, difficulty in performance authentication, and reduce the product field and life time. LPTPG(Low Power Test Pattern Generator) structure consists of m-bit counter, low power linear feedback shiftregister (LP-LFSR),NOR-gate structure, gray counter, and XOR-array. Different types of techniques arepresented in the literature to control the power consumption. These paper includes algorithms for test schedulingwith minimum power, techniques to reduce more power, techniques for reducing power during BIST(Built-InSelf-Test) technique. The generated test patterns are used to test the synchronous pipelined 4x4 and 8x8 Braunarray multipliers.
