期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
期号：NCFCSPS
页码：264
出版社：S&S Publications
摘要：The testing architecture is mainly used in all type of real world application architectures and thusthe architecture is to modified based on the enhancement purpose.The VLSI technology is to optimize the anytype of testing architecture.So the modification process is used to the VLSI technology.Nowadays the designand testability process is mainly important for the any large screening VLSI circuits. In existing system theydevelop the different DfT mechanisms,one for launch –off shift ,one for launch –off capture and one for mixedat speed testing.Because more power consume the launch- off capture and launch –off shift operation in VLSItesting circuits.Our proposed system is T– algorithm based enhance test sequence architecture.T-algorithm isused to identify the fault in the circuit and reduce the clock function.A scan sequence for one block is likely todetect fault in other blocks.So we optimize the test pattern using modified algorithm.It does not require scanenable to change the speed.It reduce the power consumption.
关键词：T-algorithm;Launch off capture;Launch off shift
