期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
期号：NCFCSPS
页码：271
出版社：S&S Publications
摘要：In this paper, we present a carry skip adder(CSKA) structure that has a higher speed yet lowerenergy consumption compared with the convention alone. The speed enhancement is achieved by applyingconcatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA)structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-ORInvert(AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized withboth fixed stage size and variable stage size styles, where in the latter further improves the speed and energyparameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers thepower consumption without considerably impacting the speed, is presented. This extension utilizes a modifiedparallel structure for increasing the slacktime, and hence, enabling further voltage reduction. The proposedstructures are assessed by comparing their speed, power, and energy parameters with those of otheraddersusinga45-nm static CMOS technology for a wide range of supply voltages. The results that are obtainedusing HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy,respectively ,compared with those of the Conv-CSKA. In addition, the power–delay product was the lowestamong the structures considered in this paper, while its energy–delay product was almost the same as that ofthe Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations onthe proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latestworks in this field while having a reasonably high speed.
