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  • 标题:Reducing the Area of A Chip Using QCA with X-Bit × 32-Bit SRAM
  • 本地全文:下载
  • 作者:Inba Manimegalai.J ; P.Priya Dharsini
  • 期刊名称:International Journal of Innovative Research in Science, Engineering and Technology
  • 印刷版ISSN:2347-6710
  • 电子版ISSN:2319-8753
  • 出版年度:2016
  • 期号:ICMEET
  • 页码:57
  • 出版社:S&S Publications
  • 摘要:Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technologyon the nano scale has a promising future; QCA is an interesting technology for building memory. The proposed designand simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presentedto implement a static random access memory (SRAM). My project presents the design and simulation of a 16-bit × 32-bit SRAM with a new structure in QCA. Since QCA is a pipeline, this SRAM has a high operating speed. The 16-bit ×32-bit SRAM has a new structure with a 32-bit width designed and implemented in QCA. It has the ability of aconventional logic SRAM that can provide read/write operations frequently with minimum delay. The 16-bit × 32-bitSRAM is generalized and an n × 16-bit × 32-bit SRAM is implemented in QCA. Novel 16-bit decoders andmultiplexers (MUXs) in QCA are presented that have been designed with a minimum number of majority gates andcells. The new SRAM, decoders, and MUXs are designed, implemented, and simulated in QCA using a signaldistribution network to avoid the coplanar problem of crossing wires. The QCA-based SRAM cell was compared withthe SRAM cell based on CMOS. Results show that the proposed SRAM is more efficient in terms of area, complexity,clock frequency, latency, throughput, and power consumption.
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