期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2013
卷号：2
期号：3
页码：639
出版社：S&S Publications
摘要：In this paper, We present a high performance adder for low power application. Carry Select Adder(CSLA) is known to be the fastest adder among the conventional adder structures. It is used in many data processingunits for realizing faster arithmetic operations. From the structure of the CSLA, it is clear that there is scope forreducing power consumption and delay in the CSLA. This work uses a simple and efficient gate-level modification tosignificantly reduce the power and delay of the CSLA. Based on this modification, 16-bit CSLA architecture have beendeveloped and compared with the regular CSLA architecture. The results analysis shows that the proposed CSLAstructure is better than the regular CSLA.
关键词：Application-specific integrated circuit (ASIC); Conventional Adder; CSLA; Low power
