Flattening of silicon wafers.
Dobrescu, Tiberiu Gabriel ; Nicolescu, Adrian Florin ; Pascu, Nicoleta 等
Abstract: Most of today's IC (integrated circuit) chips are
made from 200 mm or 150 mm silicon wafers. It is estimated that the
transition from 200 mm to 300 mm wafers will bring a die cost saving of
30-40%. A series of processes are required to manufacture high quality
silicon wafers. As one of processes to flatten silicon wafers
simultaneous double side grinding (SDGS) has a great potential to meet
the demands for high quality wafers at low cost. This paper reviews
manufacturing process flow for silicon wafers using SDGS and lapping.
The interaction effects of three process parameters (wheel rotation
speed, chuck rotational speed and federate) with surface roughness and
grinding marks are presented
Key words: silicon wafers, lapping, grinding, polishing, flattening
1. INTRODUCTION
Manufacturing of silicon wafers starts with growth of silicon
ingots. A sequence of processes is needed to turn an ingot into wafers
(Dobrescu & Dorin, 2008). This typically consists of following
processes:
* Slicing, silicon ingot into wafers of this disk shape;
* Edge profiling (chamfering), to chamfer the peripheral edge
portion of the wafer;
* Flattening (lapping or grinding), to achieve a high degree of
parallelism and flatness of the wafer;
* Etching, to chemically remove the damage induced by slicing and
flattering without introducing further mechanical damage;
* Rough polishing, to obtain a mirror surface on the wafer;
* Fine polishing, to obtain final mirror surface.
Two processes can be used to flatten the sliced wafers: lapping and
simultaneous double side grinding (SDSG).
The lapping operation is shown in figure 1.
The loaded wafers are then lapped by the abrasive slurry (typically
a mixture of alumina and glycerin) injected between two lapping plates
rotating in opposite directions.
The lapping operation would generate sub surface damages in silicon
wafers, which need to be removed by its sub sequent processes.
Simultaneous double side grinding is illustrated in figure 2. A pair of
diamond cup wheels is located on the opposite side of a rotating silicon
wafer. Both side of the rotating silicon wafer are ground simultaneously
by the two wheels, which are synchronously fed towards the wafer.
Table 1 compares lapping and SDSD in five aspects. It can be seen
that SDSG is better in almost every aspect.
[FIGURE 1 OMITTED]
[FIGURE 2 OMITTED]
2. PROCESS FLOWS USING SDGS
SDSG was introduced into semiconductor industry in 1990s (Li et
al., 2006). The diamond grinding wheels with different mesh size were
used for different process flows:
* Slicing--SDSG--Lapping--Chamfering--Polishing;
* Slicing--SDSG--Lapping--Etching--Polishing;
* Slicing--SDSG--Chamfering--Etching--Polishing;
* Slicing--SDSG (fine)--Chamfering--SDSG (second)
Etching--Polishing;
Since the main purpose of the coarse SDSG is stock removal, the
diamond grits in the course wheels have large size (mesh # 300-2000).
The mesh size of the wheels used in the fine SDSG process is in the
range of# 2000-10000.
The bond materials for the SDSG wheels could be resin, metal or
vitrified ceramic (Chidambaram et al., 2003).
3. THE EFFECTS OF PROCESS PARAMETERS ON GRINDING
Grinding marks (figure 3), or grinding linear are the traces left
by the grinding wheel on the wafer surface A (figure 3) and the
"cress-cross" on the wafer surface B (Sun et al., 2004). In
this paper only the distance between the adiacent lines of wafer surface
A will be presented. Development of the model in this paper is based on
the assumption that the grinding wheel behaves like a single-point tool.
Two output variables are registered: grinding marks and surface
roughness.
The major requirement for fine grinding of silicon wafers include:
the grinding force should be low and constant; the grinding wheel should
have a reasonable life; the ground wafers should have very good
flatness; this usually means sub micron total thickness variation;
surface and subsurface damage should be minimized (Dobrescu et al.
2009). The results on grinding marks are including in Table 2. We obtain
the mathematical model for dependence. Actual grinding mark distance
(GND) of wheel speed and respectively of wafer speed.
GMD = -0.01[n.sub.w] + 51.685 (1)
GMD = 0.45[n.sub.WF] - 11.5 (2)
The distance between the grinding marks (GMD) decreases as the
wheel speed [n.sub.W] increases. The effect of wheel speed is stranger
at the high level of wafer speed for each output variable.
[FIGURE 3 OMITTED]
Three process parameters are chosen to study their effects and
interactions: the rotational speed of the grinding wheel, the rotational
speed of the wafer and the federate of grinding wheel towards the wafer.
The results on surface roughness are included in Table 3. Surface
roughness of the ground surface is measured along a direction
approximately perpendicular to the grinding lines. The experiments are
conducted on a Nanogrinder, Grinding Machines Nuremberg. The grinding
wheel used is a diamond cap wheel. The grit size is mesh # 1200 and the
diameter of the wheel is 300 mm. The instrument used is a Surf analyzer
5000. The measurement is done at approximately the same location for
each wafer. The main effects of wheel speed [n.sub.W] and feed rate S
are significant. Lower wheel speed and higher feed rate produce rougher
surface as indicated the mathematical models:
[R.sub.a] = -0.014[n.sub.W] + 143 (3)
[R.sub.a] = 100S - 25 (4)
4. CONCLUSION
The following conclusions can be drowning:
* When the two grinding wheels rotated in different directions the
surface on one side of the wafer was different from the other side. This
was a limitation for SDSG if the identical wafer surface on both sides
were required. But, the limitation could be reduced when the wheels
rotated at a high speed report [n.sub.W]/[n.sub.WF] >> 1.
* Lower wheel speed and higher feed rate produce rougher surface.
* The distance between the grinding marks GMD is determined by
wheel speed and wafer speed through the equation (1) respectively (2).
* In silicon wafer manufacturing, the removal amount of the
subsequent polishing process to be large enough to eliminate all
grinding marks generated in the SDSG operation.
Further reduction of polishing amount necessitates optimization of
the grinding process so that the grinding marks can be eliminated with
minimum amount of polishing
5. REFERENCES
Chidambaram, S.; Pei, Z. & Kassir, S. (2003). Fine grinding of
silicon wafers: a mathematical model for grinding marks, In:
International Journal of Machine Tools & Manufacture, No. 43, pag.
1595-1602
Dobrescu, T. & Dorin, A. (2008). Flattening Process of Silicon
Wafers, Annals of DAAAM for 2008 & Proceedings of the 19th
International DAAAM Symposium, 22-25th October 2008, Trnava, Slovakia,
ISSN 1726-9679, ISBN 978-3-901509-68-1, Katalinie, B. (Ed.), pp.
0375-0376, Published by DAAAM International Vienna, Vienna
Dobrescu, T.; Enciu, G. & Nicolescu, A. (2009). Selection of
Process Parameters in Grinding Ceramics, Annals of DAAAM for 2009 &
Proceedings of the 20th International DAAAM Symposium, 25-28th November
2009, Vienna, Austria, ISSN 1726-9679, ISBN 978-3-901509-70-4,
Katalinic, B. (Ed.), pp. 0361-0362, Published by DAAAM International
Vienna, Vienna
Li, Z.; Pei, Z. & Fisher, G. (2006). Simultaneous double side
grinding of silicon wafers: a literature review, In: International
Journal of Machine Tools & Manufacture, No. 46, pag. 1449-1458
Sun, W.; Pei, Z. & Fisher, G. (2004). Fine grinding of silicon
wafers: a mathematical model for the wafer shape, In: International
Journal of Machine Tools & Manufacture, No. 44, pag. 707-716
Tab. 1. Comparison of different approaches for flattening
silicon wafers
Characteristics Lapping SDSG
Waviness removal Very good Good
Throughput Low High
Consumable cost per wafer High Low
Automation level Low High
Environmental benignity Poor Good
Tab. 2. Grinding mark distance data
Grinding mark
Wheel speed Wafer speed Feed rate distance
+ + + 22.39
+ + - 22.28
+ - - 5.53
- - + 12.98
- + + 51.08
- + - 52.18
Tab. 3. Surface roughness data
Surface roughness
[R.sub.a] [nm]
Wheel Wafer
speed speed Feed rate Wafer 1 Wafer 2 Wafer 3
+ + + 99 98 93
+ + - 105 96 90
+ - - 82 86 79
- - + 170 160 182
- + + 127 131 129
- + - 92 96 88