On hard to detect bridging fault.

Bucur, Ion ; Boiangiu, Costin-Anton ; Constantin, Nicolae 等

1. INTRODUCTION

The advent of deep-submicron (DSM) designs has created new difficulty in clock skew and power delivery, while the latest nanometer technologies have demonstrated that defects are located predominantly in routing. Inductive fault analysis of actual circuits suggests that bridging faults account for thirty to fifty percent of all faults. Several studies also did show that most silicon defects exhibit bridging fault behavior and test strategies that use simple fault model, such as single stuck-at, do not satisfy the growing test quality requirements (Pomeranz et al., 2004). Other test approaches, such as delay and [I.sub.DDQ] testing, are increasingly used for manufacturing testing of integrated circuits. Such test policy detects, in general, some sole defects. Although, [I.sub.DDQ] testing has been successfully used for detection of shorts for a long time, the efficiency of this method in complex deep sub-micron circuits has recently become questionable (Ingelsson et al., 2008). Consequently, a significant part of the testing must rely on other approaches.

2. BRIDGING FAULT MODEL

The bridging fault model, assumes that two or more wires are connected, but not intended to (Abramovici et al., 1994), by a resistive short line between them, which could be caused by a piece of metal from the sputtering process (Figure 1). For a shorted line u, one have to distinguish between the value one could actually observe on u and the value of u as determined by its source element; the latter is called driven value. A short circuit between signal 0 and signal 1 may change both signals to 0. This is called a wired-AND bridging fault because the resulting faulty signal can be obtained by an AND operation.

[FIGURE 1 OMITTED]

[FIGURE 2 OMITTED]

If on the other hand the resulting signal is 1 it is called a wired-OR bridging fault. Bridging faults models are capturing device faults caused by short between circuit connections. In order to simulate the resistive bridging fault model (Polian et al., 2005) it was used Berkeley Predictive Technology Model and BSIM4. This bridging fault model is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in those technologies. There are two current models for wires shorted together: wired-AND/wired-OR fault model, and the Dominant Fault Model.

Bridging faults in CMOS technology require more complicated models. Whereas the stuck-at fault model assumes that a cell input or output is always tied to a fixed value, this bridging fault model assumes that one gate will dominate the value driven on the other net via the electrical path through the resistive short ([R.sub.sh]). If one net dominates, then the other may have an incorrect logic value at one or more of its fanouts. In Fig. 2 is presented a general model of a bridging fault between two lines u and v, inducing a wired-function. Such bridging fault is noted by (u, v) and the function introduced by the bridging fault is noted by Z(u, v). The fanout of Z is the union of the fanouts of the shorted signals. Note that the values of u and v in this model are their driven values but these are not observable in the circuit. Induced wired-function Z has the property that Z(a, a) = a. However, value of Z when lines u and v have opposite values depends only on the technology. Bridging faults may affect device operation current, output voltage levels, and output signal timing. This study focuses on characterization of undetectable bridging faults applied to induced wired-AND/wired-OR fault model. Among the bridging faults, the undetectable ones are still more difficult to test, for obvious reasons, but their invalidating effect on complete sets of tests designed for stuck-at faults is making them separate target (Jansen, 2003). Undetectable faults are, generally, due to re-convergent fan-out and redundant logic.

3. BOOLEAN DIFFERENCE APPROACH

Following two propositions are describing dependencies of p internal functions of Boolean scalar function f involved in bridging fault inducing wired-AND, and respectively wired-OR.

Proposition 1. Let [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] be p lines in a combinational circuit C implementing scalar function f, and let note with [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] local functions of these p lines.

Then, a bridging fault inducing a wired-AND between lines [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] is undetectable in C, if and only if:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1)

Proof: One could remark that wired-AND between lines [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] introduces function [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] in network C. It could be remarked that faulty function [f.sup.*] has now this form. [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII].

One can start the proof considering exclusive-disjunctive expansion (Thayse, 1981) of function f (x, y):

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (2)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (3)

Using last term in ring sum of (3), and using expression of z:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (4)

If bridging fault between lines [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII], equivalent of a wired-AND, is undetectable then, this identity hold:

f(x,y) = [f.sup.*] (x, z x z x ... x z) = [f.sup.*] (x, z) (5)

And, taking in account that bridging fault is undetectable, it results:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (6)

The proof of the if part of Proposition 1, is finished. If expression (1) is true, then it results that:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (7)

Using notation [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII], it results that f(x, y) = [f.sup.*] (x, z), i.e. bridging fault inducing a wired-AND, between lines [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII], is undetectable. It finishes up second part (only if) of the proof. Considering p = 2, then relation (1) becomes:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (8)

Using the Boolean difference form one could re-write (9):

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]. (9)

Obvious [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] depends only on x and [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] depends only on x and [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]. Using an exclusive-disjunctive expansion it results for both Boolean differences:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (10)

For p = 2, relation (10) represents necessary and sufficient conditions of bridging fault undetectably when bridging fault, inducing an equivalent wired-AND, occurs between only two internal lines in circuit C. Similar conditions holds for bridging fault, inducing wired-OR, between p internal lines in combinational circuit C:

Proposition 2. Let [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] be p lines in a combinational circuit C implementing scalar function f and let note with [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] local functions of these p lines. Then, a bridging fault inducing a wired-OR between lines [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] is undetectable in C, iff:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (11)

From (11), for p=2 it holds this relation:

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]. (12)

Expressions (10) and (12) derived from (1) and respectively (11) are same as formulas suggested in (Kodandapani & Pradhan, 1980) but, without proofs. It makes both Proposition 1 and Proposition 2 generalizations of these formulas.

4. CONCLUSION AND FURTHER RESEARCH

Actual results are able to identify possible undetectable bridging faults before placement and layout. Known computing methods are suitable for low complexity bridging faults. This analytical tool will be developed by adding applications able to, efficiently, compute large Boolean differences.

5. REFERENCES

Abramovici, M.; Breuer, M.A., & Friedman, A.D. (1994). Digital System Testing and Testable Design, Wiley-IEEE Press, ISBN-10: 0780310624

Ingelsson, U.; Al-Hashimi, B.M., & Harrod, P. (2008). Variation Aware Analysis of Bridging Fault Testing. Proc. Asian Test Symposium, pp. 206-211, ISBN 9780769533 964, Saporo, Japan, Nov. 2008, IEEE Computer, USA

Jansen, D. (Ed.). (2003). The Electronic Design Automation Handbook, Springer, ISBN: 978-1-4020-7502-5, USA

Kodandapani, K.L., & Pradhan, D.K. (1980). Undetectability of Bridging Faults and validity of Stuck-at Fault Test Sets. IEEE Transactions on Computers, Vol. C-29, No. 1, (January, 1980) pp. 55-59, ISSN 0018-9340

Polian, I.; Engelke, P., Becker, B., Kundu, S., Galliere, J.-M., & Renovell, M. (2005). Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies, Proc. of the 23rd VLSI Test Symposium, pp.343-348, ISBN 0769523145, Palm Springs, CA, USA, 1-5 May 2005, IEEE Computer Society

Pomeranz, I.; Reddy, S., & Kundu, S. (2004). On the characterization and efficient computation of hard-to-detect bridging fault. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.23, No 12, pp.1640-1649, ISSN: 02780070

Thayse, A. (1981). Boolean Calculus of Differences (Lecture Notes in Computer Science), Springer-Verlag, ISBN-10: 3540102868, Germany