Effective approaches towards design of DDCSRC for SDR.

S., Sophia ; Suganthi, M.

Introduction

SDR aims to replicate hardware functions in software running on a generic platform. In so doing many problems associated with hardware implementations are avoided. In addition the transmitter chains can easily be changed to accommodate varying standards. So the idea of SDR requires an expansion of digital signal processing towards the antenna.

Many analog techniques for radio design have thus proven to be insufficient and unsuitable for SDR, which have taken recourse to digital hardware. Sinusoidal signals are typically used in many of the signal processing steps, such as modulation, pulse shaping and filtering.

Analog frequency techniques are based on bulky analog devices such as quartz crystals, inductors, capacitors and mechanical resonators. Digital techniques began to gain prominence in communication systems because of their superior accuracy and immunity to noise. Direct Digital Synthesis (DDS) techniques generate signals directly in discrete time. Any arbitrary waveform can be generated for digital communication systems, as the amplitude, frequency and phase can be varied to create a modulated signal. For converting the received signal to base band, the need of efficient high-speed digital converters arises.

Software Defined Radio

Software defined radio is often described as a radio whose functionality is extensively defined in software, and with the placement of data converters as close as possible. Flexibility of radio terminal to adapt to different system or to advances in services or technology is made possible by using reconfigurable hardware such as Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA). The flexibility relies on the radio to be wideband in nature and as linear as possible, so as to minimize distortion of the signal. As analog to digital converter (ADC) moves closer to the antenna more radio functionalities can be written in software and embedded in programmable logic. However, ADC performance is not still sufficient enough to digitize the RF functions. In particular the input analog bandwidth, sampling rate, dynamic range and resolution need considerable amount of improvement if wide front end and sampling at RF are to become reality.

Performance of SDR can be well understood by comparing with conventional radio system. In traditional SHR, RF signal from an antenna are received at an antenna and it goes through a band pass filter. Conversion from the transmitted RF to Intermediate Frequency (IF) is accomplished by multiplying the RF by a sinusoidal Local Oscillator (LO) signal in a mixer.

It is difficult to implement a broadband SHR, because the analog filters are usually fixed narrowband filters. In addition, analog components are subject to thermal variations and aging effects and also have problem of manufacturing consistency and require labor intensive and alignment. SDR have several advantages over today's hard-wired radio. The most obvious advantage is flexibility.

SDR receiver consists of an antenna, an analog RF section, DDC and a detector shown in figure1. The analog RF section is sometimes called the RF front-end, while the DDC is known as the digital front-end. The fundamental part of SDR receiver is the Direct Digital Converter (DDC).

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For the 2Mps transmission the modulation form is rotated Differential Encoded Quadrature Phase-Shift Keying ([pi]/4 DQPSK). For the 3Mbps transmission the modulation form is differentially encoded 8-ary Phase Shift Keying (8 DPSK). The guard sequence and the synchronization sequence are inserted to allow modulation switching in the transmitter and the demodulation in the receiver.

There are three generations of SDR receivers available. In the second generation of receivers sampling and quantization occur prior to Quadrature sampling. Here down conversion is done by IF sub sampling or Direct Conversion. In Direct Conversion SDR, RF signals are converted directly into base band by a Quadrature mixer. The Mixers output In-Phase (I) and Quadrature-Phase (Q) signals, which are then lowpass filtered and gain controlled before they are digitally sampled. In direct conversion SDR, analog filter passes a broad frequency range and a digital filter can select a desired band within that range. This technique is very useful when multiple standards using different carrier frequencies and different bandwidth have to be received by a single device.

SDR can be applied to all areas of communication and broadcasting. Two representative applications are cellular phone and wires LAN.

Comparision of Analog and Digital Signal Synthesis

Analog signal generation techniques include direct analog synthesis (DAS) and PLL method. DAS is limited by its size, cost and power consumption, making it difficult to use in portable equipments. Analog PLL have inherently slow frequency switching times due to loop filter settling delay.

DDS overcome most of the problems associated with analog signal generation. DDS is superior in terms of precision, ease of implementation and flexibility, which leads to its widespread use in wireless communication. DDS can implement sub-hertz resolution using fraction of the hardware needed by the analog synthesizer.

Using DDS it is possible to set the frequency of the output waveform more precisely than analog technique. In analog frequency is controlled by analog components, resulting in poor stability, poor frequency resolution, digital tuning.

Fine frequency steps are easily achieved easily with DDS because of relatively small increase in circuit complexity. When a frequency is executed in a DDS, output is smooth and transient free. Switching frequencies within microseconds can be achieved with DDS.

The main disadvantages of DDS include spurious frequencies in the output signal and a relatively smaller bandwidth for the output.

Design of Digital Down Converters

A fundamental part of any communication systems is digital down conversion (DDC). Digital radio receivers often have fast ADC converters delivering vast amounts of data. But in many cases the signal of interest represents a small portion of that bandwidth. So a DDC should allow more intensive processing to be performed on the signal of interest and discard the rest of data. The block diagram of DDC is shown in figure 2.

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A DDC works by shifting the bandwidth of interest to baseband by multiplying the received signal by the original carrier, this works on the simple mathematical principle:

FREQUENCY(A) * FREQUENCY(B) = FREQUENCY(A-B) + FREQUENCY(A+B)

A DDC is typically used to convert an RF signal down to baseband. It does this by digitizing at a high sample rate and then using purely digital techniques to perform the data reduction.

There are two basic approaches for generating signals directly from digital hardware. The first is commonly referred as ROM--LUT approach, which can also be used to generate sinusoidal signal. The sampled values of sine waveform are stored in ROM and are output periodically through a DAC to generate the output waveform. If an arbitrary waveform is to be generated, ROM--LUT is often used method.

CORDIC method provides a convenient approach using FPGA to compute sinusoidal functionality. CORDIC algorithms implement transcendental functions with out using a multiplier and with only a minimal LUT.

ROM LUT based DDC

The ROM LUT approach uses sampled values of a periodic function stored in ROM. Every clock cycle, a value of the periodic function stored in the ROM is output through a DAC generate the synthesized signal. The signal obtained at the output of the DAC is passed through LPFs and amplifier to obtain the final output analog waveform.

DDS based function generators are based on a single crystal oscillator, which generates a reference clock frequency. The structure of a DDS system using a ROM LUT is shown in figure 3. The adder and register functions as an accumulator and increments the output value by [DELTA]r at each clock cycle. [DELTA]r is defined as free setting word.

[FIGURE 3 OMITTED]

The output of he accumulator takes the form of an adder used by a ROM-LUT that contains the waveform samples. The number of clock cycles needed to step through the entire ROM LUT defines the period of the waveform. The waveform period is determined by [DELTA]r. The LUT holds the digital representation of the desired waveform, which is made of digital words that defines the amplitude of the waveform as a function of phase. The address generated by the adder represents the phase value of the waveform.

The address generator sequentially reads the table of digital values out of memory and passes them to the DAC to generate the output waveform. The DAC changes each of these digital words into an analog voltage, fed through filters to reduce the distortion and amplifiers to produce an analog signal. The period of the output waveform is based on the phase increment value [DELTA]r and the frequency of the clock signal [F.sub.clk].

To output a particular frequency, the proper phase increment value must be loaded into the accumulator. The original address is increased by the phase increment and is used to index the ROM LUT. According to nyquist sampling criteria, the maximum value of low pass output frequency, [F.sub.out]=[F.sub.clk]/2

The desired resolutions of this frequency output from the ROM look up table affects the size of the accumulator and also the size of LUT. The frequency resolution is given by

[DELTA]F=[F.sub.clk]/ACM

where Fclk is the system clock and ACM is the size of the accumulator. ACM=[2.sup.N],

where N is number of bits in accumulator. Since the transformation in the LUT is non linear, the output frequency,

[F.sub.out] = [DELTA]r [F.sub.clk]/ACM

The size of phase increment can be calculated as [DELTA][PHI] = ([F.sub.out]/[F.sub.clk])*ACM where [F.sub.out] being the desired output frequency in the ROM-LUT. The spectral purity and sideband noise are the major drawback of the DDS system.

The sources of spurious signal are amplitude truncation, phase truncation and DAC non-linearity.

For high resolution (n bits) it requires a look up table of [2.sup.n] * n bits resulting in high power consumption, low speed and increased cost.

CORDIC based DDC

Another way of performing down conversion without the sine or cosine look-up tables is the CORDIC (Co-Ordinate Rotation Digital Computer) algorithm. The CORDIC algorithm was developed in 1959 by Volder to convert between Cartesian and polar co-ordinates. It is implemented as set of iterative equations that model and control translations along a simple geometric shape. It translates a point along the unit circle to implement cosine, sine, arctangent and magnitude functions. These functions correspond to mapping between rectangular and polar coordinate systems. The block diagram of CORDIC-BASED DDC is shown in the figure 4.

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In the circular rotation mode the CORDIC computes the Cartesian co-ordinates of the target vector [v.sub.n] =[[x.sub.n], [y.sub.n]].sup.T] by rotating the input vector [v.sub.o] =[[[x.sub.o], [y.sub.o]].sup.T] by an arbitrary angle[PHI]= [z.sub.o]. The vector rotation is realized by performing a sequence of successively decreasing elementary rotation angles [[PHI].sub.i]= [+ or -] arctan ([2.sup.-i]) for i=0,1,... n-1.

After n iterations the CORDIC equations result in [x.sub.n] = [A.sub.n] [[x.sub.o] cos([z.sub.o]) - [y.sub.o] cos([z.sub.n])] [y.sub.n] = [A.sub.n] [[y.sub.o] cos([z.sub.o]) + [v.sub.o] cos([z.sub.n])] [z.sub.n] = 0

where

n

[A.sub.n] = [product] [check](1+[2.sup.-2i])

i=0

The accuracy is determined by number of iterations and the word length of the CORDIC processor.

At each clock interval, [y.sub.o] is loaded with the current sample SBP (k) of an IF input signal and [z.sub.0] with the current sample [PHI](k). [x.sub.o] is set to zero. After n=1 iterations the CORDIC provides the sample I(k) and Q(k) of the down converted Inphase and Quadrature phase signal with a resolution of approximately n bits. In order to achieve this, only a very small look up table is needed. It contains the (n+2) basic rotation angles.

The CORDIC can be implemented using pipelined architecture. Thus, the CORDIC DDC becomes suitable for high speed applications. An additional advantage of such implementation is that there is no need for a look-up table anymore, since the invariant elementary rotation angles can be hard-wired to each stage.

Sample Rate Conversion

Sampling of BandPass(BP) signal can be carried out at rates lower than conventional low pass Nyquist sampling rate, causing intentional aliasing. Bandpasss sampling can allow for received signal to be digitized closer to antenna using manageable sampling rates and hence could be favorable for down conversion in SDR.

A couple of filtering techniques are available for down sampling of signal,

Cascaded Integrator Comb (CIC) filters

Polyphase Decimation filter

Polyphase Raised cosine filter

CIC is a more resource friendly implementation of antialasing filter than polyphase filter.

The power response of CIC filter is,

H([e.sup.2j[pi]f/M]) = p(f)= {sin ([pi]f)/ sin([pi]f/M)}N

Results & Discussions

In this section simulation results are presented to compare the performance of the CORDIC & ROM LUT based algorithms for the design of DDC. The programs are simulated using MATLAB. The programs are executed for [pi]/4 DQPSK Modulation scheme. Channel is considered to be AWGN with gain=1, so that it acts as an ideal channel.

Bit Error Rate (BER) and Average Bit Error Rate (AvBER) is calculated for different SNR values. Graphs 1,2,3,4 shows the plot of BER, AvBER vs number of iterations for both CORDIC and ROM- LUT methods.

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The results shows that for CORDIC DDC BER remains a constant value of 0.28 for iterations n = 12, 13, 14 & 15. So the optimum number of iteration required for CORDIC is 12. Hence increasing the number of iterations does not have any effect in CORDIC DDC.

In ROM-LUT method for the same number of iterations BER is a varying value from 0.28 to 0.51.While analyzing the AvBER vs iterations, we find that for CORDIC it is 0.028 and ROM it is 0.0392.

Conclusion

In this paper two methods CORDIC DDC, ROM LUT DDC method for Digital down conversion are proposed. From the results we find that CORDIC based method overcomes the drawbacks of ROM LUT that requires very large ROM table to achieve high resolution. CORDIC method helps to save chip area, power consumption and cost. Since CORDIC can be easily implemented using pipelined architecture, it is suitable for high-speed wireless application.

CIC is most suited for SDR implementation since:

* No multipliers are required

* No storage is required for filter cofficeint

* Structure of CIC filter is regular and it has two simple blocks

* Very little complicated control is needed

References

[1] J. G. Prokis, DIGITAL COMMUNICATION, 3rd Ed.Mc -Graw Hill, 1995.

[2] Bernard Skalr, DIGITAL COMMUNICATION fundamental and Application, Prentice Hall, 1988.

[3] H. Meyar, M. Moeneclaey and S. Fechtel, DIGITAL COMMUNICATION RECEIVERS. John Wiley & Sons, 1998.

[4] D.Torrieri and K. Bakhru, " Blind adaptation using Maximin algorithm", In Proceedings of Asilomar Conf. On Signals, Systems and Computers, pp. 638642,, Nov. 2001.

[5] U. Mengaali and Aldo N. D'Andrea, "Synchronization techniques for digital receivers", Plenum Press, c1997.

[6] J. Mitola III. " Software Radio Architecture : A Mathematical Perspective",, IEEE Journal on selected areas in communications,17(4), Apr. 1999.

[7] Y. H. Hu, "The Quantization effects of the CORDIC algorithm", IEEE Transactions on signal processing, Vol. 40, pp. 834-844,Apr.1992,

Sophia S (1) and M Suganthi (2)

(1) Lecturer, Dept. of ECE., Sri Ramakrishna Engg. College, Coimbatore, India sofia_sudhir@yahoo.com

(2) Asst. Professor, Dept. of ECE., Thiagarajar College of Engg., Madurai, India