FPGA based multiprocessor core for processing of sensor signals.

Kamat, Rajanish K. ; Shinde, Santosh A. ; Shelake, Vinod G. 等

Introduction

As sensor based applications rapidly increase in complexity, it becomes imperative to embed a greater degree of onchip processing by using a suitable microcontroller. Such applications which typically involves multiple sensor measuring different types of parameters, dictates that the ADC support a variety of sampling, conversion and triggering options. The performance bottleneck is encountered if the implementation is based on a single microcontroller owing to sequential processing, non-customized architecture to the individual sensor requirements and increased burden in post processing the sensor signal prior to the further acquisition of signal from other sensor. Moreover most of such multi-channel data acquisition systems face a typical problem of sampling instants dispersed in time. Distributed processing using different microcontrollers have been investigated by researchers to overcome the above mentioned bottlenecks. However, in such multi-microcontroller systems issues such reliability, inter- processor communication are questionable due to the physically dispersed cores. The present communication reports a FPGA based multi-microcontroller core suitable for multi-sensor data acquisition systems. The core is based on picoblaze[1] implemented on Xilinx SPARTAN III FPGA [2].

Design problem

The schematic of the implementation is show in figure 1. Three cores of the Picoblaze are integrated on Spartan III FPGA. The core 1 is dedicated for the ADC- DAC interfacing typically required for processing the algorithms such as velocity or displacement control. The second core acquires the sensor signal and inturn drives the optocoupler based triac unit for power control. The third core is meant for data acquisition and displaying the acquired data on a 16 x2 LCD. The top level i.e. behavioral model was developed in VHDL. Assembly code was developed separately using the picoblaze IDE for individual processor cores. The same was executed using KCPSM3.exe. The KCPSM3 VHDL file, generated ROM file are added to the project environment of Xilinx webpack and dumped to Spartan III FPGA using JTAG programmer. Details of methodology are given in KCPSM3 manual [3].

[FIGURE 1 OMITTED]

Results and Discussion

The implemented design is a classic example of scenario specific microcontroller implementation. The results are summarized in table I. Total equivalent gate count for the design is 224,651. The top level RTL schematic as appeared in XILINX webpack version 6 is shown in figure2. The hierarchical RTL version of the design is shown in figure 3. The implementation offers several advantages. In the first place, the individual processor cores are customized to the interface requirements which results into a hardware efficiency. This eliminates the bottleneck of latency from processor side due to tuning of processor architecture to the intended off-chip interface. The multiple processor implementation also off-loads the processing and data storage requirements which otherwise would have been taken care by the single processor.

This would have been definitely resulted into higher latency. Another possible advantage of the reported architecture is storage of constants and their on the fly updating for calibration of the data acquired from the sensor. For example the thermistor Steinhart-Hart coefficients can be stored and updated with the changing range of the temperature measurement setup. The implementation offers a very good power budgeting as the clock per individual processor is chosen based on the actual processing speed requirement. This feature is very difficult in a general purpose microcontroller as the choice of the clock is dictated by the slowest module in the overall system. Yet another advantage is the enhanced pin count that realizes the possibility of connecting good number of sensors making the implementation ideal for processing of sensor arrays. The mutlicore circuit reported provides a very potent platform for processing and analyzing the data from multiple sensors. Use of soft IP core facilitates rapid design and the FPGA implementation realizes rapid prototyping. The implementation has many potential applications in measurement and processing of temperature sensors, PIR detection, gyroscopes, glass break detection etc. to name a few.

[FIGURE 2 OMITTED]

[FIGURE 3 OMITTED]

References

[1] PicoBlaze Soft Processor homepage URL: http://www.xilinx.com/ipcenter/processor_central/picoblazer/index.htm

[2] Xilinx DS099 Spartan-3 FPGA Family data sheet, URL: http://direct.xilinx.com/bvdocs/publications/ds099.pdf

[3] KCPSM3 Manual: URL: www.xilinx.com/bvdocs/userguides/ug129.pdf

[4] Acknowledgement: This work was supported by the DST-SERC Fast Track Project for Young Scientist Grant SR/FTP/ETA-14/2006 entitled "Development of FPGA based open source soft IP cores for parameterized microcontroller design" to Dr. R.K. Kamat.

Rajanish K Kamat, Santosh A. Shinde and Vinod G. Shelake

VLSI Laboratory, Department of Electronics,

Shivaji University, Kolhapur-416 004, India

Email: rkk_eln@unishivaji.ac.in

Table I : Design Summary

Design Metrics                     Figures

Logic Utilization:
Number of Slice Flip Flops         210 out of 7,168 2%
Number of 4 input LUTs             326 out of 7,168 4%

Logic Distribution:
Number of occupied Slices          288 out of 3,584 8%
Number of Slices containing only   288 out of 288 100%
  related logic
Number of Slices containing        0 out of 288 0%
  unrelated logic

Total Number 4 input LUTs          542 out of 7,168 7%
Number used as logic               326
Number used as a route-thru        12

Number used for Dual Port RAMs     48
  (Two LUTs used per Dual Port
  RAM)

Number used for 32x1 RAMs          156
  (Two LUTs used per 32x1 RAM)

Number of bonded IOBs              40 out of 141 28%

Number of Block RAMs               3 out of 16 18%

Number of GCLKs                    3 out of 8 37%