Closed loop controlled multilevel inverter with reduced harmonics.

Kumar, G. Mahesh Manivanna ; Reddy, S. Rama

Introduction

In recent years, industry has begun to demand high power equipment, which now reaches the megawatt level. Controlled AC drives in the megawatt range are usually connected to the medium-voltage network. Today it is hard to connect a single power semi-conductor switch directly to medium voltage grids. For these reasons a new family of multilevel inverter has emerged as the solution for working with higher voltage level [2].

Multilevel inverter include an array of power semiconductors and capacitor voltage sources, the output of which generates voltages with stepped waveforms with less distortion, less switching frequency, higher efficiency, lower voltage devices and better electromagnetic compatibility. The commutation of the switches permits the addition of the capacitor voltages, which reach high voltages at the output, while the power semiconductors must withstand only reduced voltage [3; 4].

The multilevel voltage source inverter's unique structure allows them to reach high voltages with low harmonics without the use of transformers [4]. The general function of the multilevel inverter is to synthesize a desired ac voltage from several levels of dc voltages.

The most attractive application of this technology is in the medium-to-high-voltage range, and includes motor drives, power distribution, and power conditioning applications. In general multilevel inverter can be viewed as voltage is synthesized from many discrete smaller voltage levels. In the literature [1] to [10], the embedded controlled multilevel inverter is not presented. In the present work, simulation and implementation of the closed loop controlled multilevel inverter is presented.

Three Level Inverter

The first practical multilevel topology is the neutral point clamped (NPC) PWM topology introduced by Nabe.et.al, in 1980. For m-level inverter, dc bus voltage is splits into 'm' levels by (m-1) series connected bulk capacitors. Here, diodes clamp the switch voltage to half the level of the dc bus voltage, which is an added advantage of this type. Figure 1 illustrates the building block of a phase-leg diode clamped three level inverter.

In this circuit, the dc bus voltage is split in to three levels by two series connected bulk capacitors [C.sub.1] and [C.sub.2]. The middle point of the two capacitors 'n' can be defined as the neutral point. The diodes [D.sub.1] and [D.sub.2] clamp the switch voltage to half the level of the dc bus voltage.

Simulation Results

The diode clamped three level inverter has been simulated using ORCAD PSPICE-software. The switching pulses and simulated output voltage waveform are illustrated in figures 2. (a) and 2. (b) respectively.

[FIGURE 1 OMITTED]

[FIGURE 2a OMITTED]

[FIGURE 2b OMITTED]

Closed Loop Controlled Multilevel Inverter

The closed loop circuit of three level inverter shown in figure 2c, output voltage of the rectifier shown in figure 2d and the output voltage of closed loop controlled multilevel inverter shown in figure 2e.

[FIGURE 2c OMITTED]

[FIGURE 2d OMITTED]

[FIGURE 2e OMITTED]

Harmonic Reduction

The output voltage of the diode clamped three level inverter is a quarter-wave symmetric stepped voltage waveform. The output voltage will have fundamental and the associated harmonics. These harmonics produce additional heating, when the output voltage of the inverter is fed to the induction motor. The harmonic reduction can be achieved by selecting proper switching angles. The Fourier series of the output is,

Vo(t) = [[summation].sup.[??].sub.[??]] Bn sln nwt (1)

Due to half wave symmetry of the output waveform, the even harmonics would be eliminated and possess only the odd harmonics. Hence the average value 'Ao' and constant 'An' are zero.

Therefore, [B.sub.n] = 4 Vs/[pi] [[integral].sup.[pi]/2.sub.[alpha]1] sin nwt d(wt) (2)

By solving we get,

[B.sub.n] = 4 Vs/n[pi] [cos n[[alpha].sub.1]] (3)

The third, fifth and seventh harmonics would be eliminated separately if [B.sub.3] = [B.sub.5] = [B.sub.7] = 0, and equation (3) gives the necessary equations to be solved.

Cos3[[alpha].sub.1] = 0; cos5[[alpha].sub.1] = 0; cos7[[alpha].sub.1] = 0;

Solving these equations, we get corresponding switching angles, therefore third, fifth and seventh harmonics would be eliminated respectively; it can be understood using the following table

 Harmonics to be     Switching Angles [alpha]1      Pulse Widths
    Eliminated              (in Degrees)          (In milli second)

Third harmonic              30[degrees]               6.66 ms
Fifth harmonic              18[degrees]                 8 ms
Seventh harmonic           12.86[degrees]              8.56ms

Third Harmonic Elimination

The third harmonic would be eliminated for switching angle [[alpha].sub.1] = 30[degrees]. This is illustrated in figure 3.

[FIGURE 3 OMITTED]

From the figure 3, it can be seen that the third harmonic has been completely eliminated, while the fifth and seventh harmonics are present.

4.2 Fifth Harmonic Elimination

The fifth harmonic was eliminated with a switching angle [[alpha].sub.1] of 18[degrees]. This is illustrated in figure 4.

[FIGURE 4 OMITTED]

From the figure 4, it can be seen that the fifth harmonic has been completely eliminated, while the third and seventh harmonics are present.

Seventh Harmonic Elimination

The Seventh harmonic was eliminated with a switching angle [[alpha].sub.1] of 12.86[degrees]. This is illustrated in figure 5.

[FIGURE 5 OMITTED]

From the figure 5, it can be seen that the seventh harmonic has been completely eliminated, while the third and fifth harmonics are present.

Hardware Implementation

The hardware is fabricated and tested with R and RL loads. The results are presented here. Driving pulses for s1 and s2 are shown in figs 8a and 8b respectively. Inverter output voltage with R load is shown in fig 8c. The inverter output voltage with RL load is shown in fig 8d.

[FIGURE 8 OMITTED]

Conclusion

The diode clamped three level inverter was simulated using orcad pspice-software and the simulation results are presented. The harmonic reduction was achieved by selecting proper switching angles. Third harmonic was eliminated with [[alpha].sub.1] = 30[degrees]. Fifth harmonic was eliminated with [[alpha].sub.1] = 18[degrees]. Seventh harmonic was eliminated with [[alpha].sub.1] = 12.86[degrees]. The hardware is tested with R and RL load. The simulation of closed loop control is achieved successfully. The experimental results coincide with the simulation results.

References

[1] Brain A. Welchko, Mauricio Beltrao de Rossoter Correa, Thamas A. Lipo, "A Three-Level MOSFET inverter for Low-power Drives" IEEE transactions on Industrial electronics, Vol51, No.3, pp.669-674, June 2004

[2] John N. Chiasson, Leon M. Tolbert, Keith J. McKenzie, Zhong Du, " A Complete solution to the harmonic elimination problem", IEEE transactions on power electronics, Vol. 19, No.2, pp. 491-498, March 2004.

[3] Jose Rodriguez, Jin-Sheng Lai and Fang Zheng, "Multilevel Inverters: A survey of topologies, Control applications," IEEE transactions on Industrial Electronics, Vol.49, No. 4, pp. 724-738, August 2002.

[4] B.K. Bose, (2003), "Modern Power Electronics and AC drives", Pearson Education (India) Pvt. Ltd.

[5] Muhammad H. Rashid (2004), "Power Electronics Circuits, Devices and Applications", Pearson Education (Singapore) Pvt. Ltd.

[6] V. G. Agelidis and M. Calais, "Application specific harmonic performance evaluation of multicarrier PWM techniques," in proc. IEEE PESC'98, vol. 1, 1998, pp. 172-178.

[7] A. Nabae, I. Takahashi, and H. Akagi, " A new neutral-point-clamped PWM inverter, " IEEE Trans. Ind. Applicat., vol. IA-17, pp. 518-523, Sept./Oct. 1981.

[8] P. D. Ziogas, "Optimum voltage and harmonic control PWM techniques for three-phase static UPS inverters," IEEE Trans. Ind. Applicat., vol. IA-16. no. 4, pp. 542-546, July/Aug. 1980.

[9] H. Patel and R. G. Hoft, " Generalized techniques of harmonic elimination and voltage control in thyristors: Part-I Harmonics elimination," IEEE Trans. Ind. Applicat., vol. IA-9, no. 3, pp. 310-317, May/June 1974.

* G. Mahesh Manivanna Kumar and ** S. Rama Reddy

Research Scholar, Sathyabama University, Tamil Nadu, India E-mail: maheshmanivannakumarg@yahoo.co.in

** Professor, Jerusalem College of Engineering, Tamil Nadu, India E-mail: Srr-victory@yahoo.com