期刊名称：International Journal of Software Engineering and Its Applications
印刷版ISSN：1738-9984
出版年度：2016
卷号：10
期号：9
页码：1-8
DOI：10.14257/ijseia.2016.10.9.01
出版社：SERSC
摘要：This paper proposes a multi-thread architecture-based Image Signal Processor (ISP). As the required image quality is gradually increasing in today's society and the image processing algorithms are becoming more diversified, the burden of calculations in the main processor such as CPU is growing bigger. To solve these problems, an ISP was designed in order to reduce the burden on the main processor by applying the multi- thread architecture and applying various image processing algorithms, allowing a high performance processing. The proposed ISP has a multi-bank cache memory that can perform the multi-thread data and instructions with a hit-save-FIFO and latency hiding unit. The proposed ISP was verified with Virtex-7 FPGA and showed about 2.4 times higher processing speed compared to the conventional DSP.
关键词：Multi-thread; Image Signal Processor; Multi-bank Cache; SIMT
