期刊名称：TELKOMNIKA (Telecommunication Computing Electronics and Control)
印刷版ISSN：2302-9293
出版年度：2016
卷号：14
期号：2
页码：464-470
DOI：10.12928/telkomnika.v14i2.3675
出版社：Universitas Ahmad Dahlan
摘要：The realization of an analog-to-digital-conversion chip has great significance in the applications of electronic products. By considering mature time–number digitization, a new multifunction digital chip with a long time delay was designed in this study on the basis of the principle of analog-to-time conversion (ATC) and the realization of long time delay. With additional resistance, capacitance, and transistors, this chip can easily realize ATC, monostable triggers, Schmitt triggers, and multivibrators. The circuit composition of this chip was analyzed, and every module design was introduced. According to the simulation result of Hspice and CSMC 2P2M CMOS (Complementary Metal Oxide Semiconductor) process database, the chip layout (1mm 2 ) design was accomplished by using CSMC 2P2M CMOS technology. Finally, the designed chip was applied in multiproject wafer flow. The flow test demonstrated that this new chip can meet design goal and is applicable to various digital integrated chip designs as an IP (intellectual property) core.
其他摘要：The realization of an analog-to-digital-conversion chip has great significance in the applications of electronic products. By considering mature time–number digitization, a new multifunction digital chip with a long time delay was designed in this study on the basis of the principle of analog-to-time conversion (ATC) and the realization of long time delay. With additional resistance, capacitance, and transistors, this chip can easily realize ATC, monostable triggers, Schmitt triggers, and multivibrators. The circuit composition of this chip was analyzed, and every module design was introduced. According to the simulation result of Hspice and CSMC 2P2M CMOS (Complementary Metal Oxide Semiconductor) process database, the chip layout (1mm 2 ) design was accomplished by using CSMC 2P2M CMOS technology. Finally, the designed chip was applied in multiproject wafer flow. The flow test demonstrated that this new chip can meet design goal and is applicable to various digital integrated chip designs as an IP (intellectual property) core.
