期刊名称：Proceedings of the Canadian Engineering Education Association
出版年度：2011
语种：English
出版社：The Canadian Engineering Education Association (CEEA)
摘要：The foundation behind asynchronous serial data communications in microprocessor-based systems is generally taught through the theoretical timing diagrams and implementation of a protocol in a laboratory setting. Although students can extract the necessary information from the timing diagram to program a selected microprocessor, they face a number of challenges during the implementation because of the lack of tools to debug and observe the output of the microprocessor incrementally. More specifically, students cannot apply some of the acquired debugging skills like the use of breakpoints or oscilloscopes because (i) programming breakpoints can confirm the logic state of a signal and sequence of events, but not the timing of events, (ii) oscilloscopes can only capture portions of timing signals, and (iii) the signals captured are not digitized, thus displaying uncertainty in noisy environments. Once the programming task is completed, the protocol is verified by transmitting a known message, with the expectation that it will be received at the other end of the serial transmission link - an approach (all-or-nothing) that can be very frustrating during a lab session. This paper presents the use of a logic/protocol analyzer to enhance learning of asynchronous serial data communications by capturing and visualizing the real timing diagrams from a laboratory unit. The use of the Saleae Logic Analyzer provides students with a visual representation of the waveforms at every stage of their design and establishes a very clear link between the timing diagrams discussed in a class and their actual implementations in the lab.
