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  • 标题:Security Design of DES Using Reversible Logic
  • 本地全文:下载
  • 作者:Shikha Kuchhal ; Rakesh Verma
  • 期刊名称:International Journal of Computer Science and Network Security
  • 印刷版ISSN:1738-7906
  • 出版年度:2015
  • 卷号:15
  • 期号:9
  • 页码:81-84
  • 出版社:International Journal of Computer Science and Network Security
  • 摘要:Reversible logic is an emerging research area. Interest in reversible logic is sparked by its applications in several technologies, such as quantum, CMOS, optical and nanotechnology. Reversible implementations are also found in thermodynamics and adiabatic CMOS. Power dissipation in modern technologies is an important issue, and overheating is a serious concern for both manufacturer and customer. One of the main benefits that reversible logic brings is theoretically zero power dissipation in the sense that, independently of underlying technology, irreversibility means heat generation. Synthesis of multiple-output functions has to be done in terms of reversible objects. This usually results in addition of garbage bits which in contrast to the non-reversible case is technologically difficult and expensive. The amount of garbage is a very important criterion for a good synthesis procedure, since in most technologies the addition of only one bit of garbage is very expensive or even impossible to implement. Minimal garbage realization may require a larger number of gates in the circuit, but it is better to have a large but working circuit than a small one that is not ready for the technology. Encryption system demands not only high security but low power consumption. Reversible logic arose more and more attention in the recent past due to its less heat dissipating characteristics. We analysis the functional module of DES system, and designed respectively a reversible circuit of a 4- bit counter and a reversible circuit of two-way shift register. By using a series of reversible device, we realized the design of reversible circuits for the functional modules.
  • 关键词:Encryption; Cryptography; Reversible logic; DES
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