期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2011
卷号：11
期号：7
页码：38-42
出版社：International Journal of Computer Science and Network Security
摘要：The continually increasing integration density of integrated circuit, with astronomical increase in fabrication cost and enormous time to market portrays important paradigm shift in next generation System ?on-Chip (SoC) design. This leads more programmable designs that can spin a wide range of applications. Hence there is a trend away from the fixed SoC to highly flexible SoC with improved time to market. The reconfigurability in SoC can be achieved either by the Programmable gate arrays [FPGA] and/or through Programmable interconnect. The emergence of static memory based FPGA that are capable of being dynamically reconfigured i.e. partially programmable during run time has been a driving force for flexible architecture. At the same time, the standardization of the intellectual property [IP] deliverables and their wide availability has started gaining importance towards expanding the possibility of reconfiguration in SoC Synthesis of SoC has become less complicated shortening design time, with the IP reuse which could be achieved by socketisation. The pre-designed and pre-verified IP blocks are obtained from the internal sources or third parties and combined onto a single chip. This arises a need of rapid integration of communication between different modules embedded in the system. The proposed design provides a solution for achieved with minimal cost of hardware and software, and improve the performance. In a Hardware design, the hardware complexity of the FIR filter is directly proportional to the tap length and the bit-width of input signal. To reduce the hardware cost, this can be figured out with iteration calculations by software, therefore, a co-design of hardware and software may produce cost-efficient FIR filters. The key design concept is to build a processor for software processing with minimum hardware resources, without sacrificing the performance of original FIR filter. The proposed design methodology can be considered as an intellectual property (IP) design for FIR filters in system-on-a- chip (SOC) environment.
