期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2010
卷号：10
期号：7
页码：110-117
出版社：International Journal of Computer Science and Network Security
摘要：Application of multiple-valued logic(MVL) in the design of digital devices opens additional opportunities. D flip-flop is a basic sequential circuit in any logic. A 4-bit counter using Multiple-valued D flip-flops is presented in this paper. D flip-flop is built by 3 input NMIN gates and has both preset and clear inputs. Quaternary multiplexer and D flip-flops are used to design the quaternary counter. The circuits being studied are optimized for power and delay at 0.18-?m CMOS process technology. The new D flip-flop designed here shows 64.33 percent improvement in dynamic power dissipation when compared to DLC based flip-flop and Q-IDEN D flip-flop. The proposed Counter circuit also exhibits less dynamic power dissipation.
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