期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2009
卷号：9
期号：3
页码：201-209
出版社：International Journal of Computer Science and Network Security
摘要：This paper presents a Genetic Algorithm (GA) based strategy to solve the problem of System-on-Chip testing. It addresses the issues like core and interconnect testing, while most of the previous works reported in the literature takes care of core testing alone. The scheduling results produced show the trade-off between the testing time and power dissipated s while shifting the test patterns and responses through scan chains. This provides a wide range of choice for the designer to select a suitable test architecture.
关键词：SoC testing; Core; Interconnect test; Scan-power; Power optimization
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