期刊名称：International Journal of Advanced Computer Research
印刷版ISSN：2249-7277
电子版ISSN：2277-7970
出版年度：2015
卷号：5
期号：18
页码：1-10
出版社：Association of Computer Communication Education for National Triumph (ACCENT)
摘要：Energy efficient test-able binary logarithmic multiplier and divider architecture using reversible logic has been reported in this paper. The focus of this paper is to avoid multiplication and division stages to reduce large layout area and make the circuit efficiently test-able. Here all the computations have been performed in radix-2 basis. Moreover to avoid the usage of large number of constant inputs, an efficient technique has been adopted. Though the procedure demands errors in the result, efforts have been made to achieve higher accuracy.
