摘要：In this paper we present PEPSY , a novel prototyping environment for multi-DSPsystems, with the primary goal to support the design and implementation of parallel digital signal processing (DSP) applications subject to various design constraints. Given a specification of the prototyping problem in the form of an application model, a hardware model and mapping constraints, PEPSY automatically maps and schedules the DSP application onto the multi-processor system and synthesizes the complete code for each processor. A detailed performance model of the parallel application is an integral part of PEPSY . Important performance parameters such as computation and communication times as well as memory consumption can be estimated prior to the implementation. PEPSY not only solves the standard mapping and scheduling problem, but it is also able to explore various important design goals for embedded systems and DSP applications such as minimizing memory and power consumption and enforcing the timeliness of tasks. Two complex case studies demonstrate the feasibility of our prototyping environment.
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