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  • 标题:HARDWARE BASED BINARY ARITHMETIC ENGINE
  • 本地全文:下载
  • 作者:N. SARANYA ; DHIRENDRA KUMAR TRIPATHI ; DR. R. MUTHAIAH
  • 期刊名称:Journal of Theoretical and Applied Information Technology
  • 印刷版ISSN:1992-8645
  • 电子版ISSN:1817-3195
  • 出版年度:2011
  • 卷号:32
  • 期号:2
  • 页码:128-134
  • 出版社:Journal of Theoretical and Applied
  • 摘要:Context Based Binary Arithmetic Coding (CBAC) is a part of JZ profile of Audio Video Coding Standard (AVS).The goal of this paper is to present the efficient hardware based binary arithmetic coder which is the main part of binarisation involved in CBAC of AVS. This paper explains about the efficient arithmetic coding involved in the video transcoding. The major concerns of using JZ profile of AVS is movie compression for high-density storage and relatively higher computational complexity can be tolerated at the encoder side to provide higher video quality. This arithmetic coder avoids the slow multiplication, here the traditional arithmetic calculation is transformed to software domain using log. The proposed arithmetic engine will give high compression gain and an efficient coding design for handling the high resolution video sequence. This is used for the effective pipelining process and increase the overall processing speed. The implementation of arithmetic coder in CABAC (Context Adaptive Binary Arithmetic Coding) architecture is satisfying the CBAC feature. The study of this paper is required to know about the process of efficient AC(arithmetic coding) and the hardware based arithmetic engine in CBAC. The CBAC engine is implemented on Xilinx Virtex-5 ML501 Board. The synthesis and simulation results are presented. The proposed architecture can work with the 31.384MHz rate.
  • 关键词:AC;CBAC;CABAC;AVS;Videotranscoding;Binarisation;Qcoder
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