By adopting the 0.35μ2P4M 3.3V standard CMOS technology created by SMIC company, this paper designs a kind of charge pump phase-locked loop (CPPLL) circuit with mixed-signal structure. By improving the phase and frequency detector (PFD), charge pump circuit (CPC), and oscillator circuit design of the PLL circuit, the clock signal used in the video decoder chips can have a more stable performance. The effective tracking range of PLL is 5 MHz ~ 7.5 MHz, the locking output is 6.75 MHz during which the clock jitter is less than 500 ps, the output waveform's duty circle is 50.1408%.